View PCA8534AH-Q900_1964181.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the pca8534a is a peripheral device which interfaces to almost any liquid crystal display (lcd) 1 with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 60 segments. it can be easily cascaded for larger lcd applications. the pca8534a is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). aec-q100 compliant for automotive applications. 2. features and benefits ? single-chip lcd controller and driver ? selectable backplane drive configurations : static, 2, 3, or 4 backplane multiplexing ? 60 segment outputs allowing to drive: ? 30 7-segment alphanumeric characters ? 16 14-segment alphanumeric characters ? any graphics of up to 240 elements ? cascading supported for larger applications ? 60 4-bit display data storage ram ? wide lcd supply range: from 2.5 v for low threshold lcds up to 6.5 v for guest-host lcds and high threshold (automobile) twisted nematic lcds ? internal lcd bias generation with voltage follower buffers ? selectable display bias configurations: static, 1 ? 2 , or 1 ? 3 ? wide logic power supply range: from 1.8 v to 5.5 v ? lcd and logic supplies may be separated ? low power consumption ? 400 khz i 2 c-bus interface ? compatible with any microp rocessors or microcontrollers ? no external components ? display memory bank switching in static and duplex drive modes ? auto-incremented display data loading ? versatile blinking modes ? silicon gate cmos process pca8534a universal lcd driver fo r low multiplex rates rev. 02 ? 1 june 2010 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 16 .
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 2 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 3. ordering information 4. marking table 1. ordering information type number package name description delivery form version pca8534ah/q900 lqfp80 plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm tape and reel sot315-1 table 2. marking codes type number marking code pca8534ah/q900 pca8534a/q900
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 3 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 5. block diagram fig 1. block diagram of pca8534a 013aaa26 8 lcd voltage selector clock select and timing blinker timebase oscillator input filters i 2 c-bus controller power-on reset clk sync osc scl sda backplane outputs display control bp0 bp1 bp2 bp3 display segment outputs display register output bank select and blink control 60 s0 to s59 sa0 v dd a0 a1 a2 pca8534a lcd bias generator v ss v lcd command decode write data control display ram data pointer and auto increment subaddress counter
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 4 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 6. pinning information 6.1 pinning top view. for mechanical details, see figure 24 . fig 2. pin configuration for lqfp80 (pca8534ah) pca8534ah s31 s10 s32 s9 s33 s8 s34 s7 s35 s6 s36 s5 s37 s4 s38 s3 s39 s2 s40 s1 s41 s0 s42 v lcd s43 v ss s44 sa0 s45 a2 s46 a1 s47 a0 s48 osc s49 sync s50 v dd s51 s30 s52 s29 s53 s28 s54 s27 s55 s26 s56 s25 s57 s24 s58 s23 s59 s22 bp0 s21 bp1 s20 bp2 s19 bp3 s18 n.c. s17 n.c. s16 n.c. s15 n.c. s14 sda s13 scl s12 clk s11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 013aaa269
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 5 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 6.2 pin description table 3. pin description symbol pin type description s31 to s59 1 to 29 output lcd segment output 31 to 59 bp0 to bp3 30 to 33 output lcd backplane output 0 to 3 n.c. 34 to 37 - not connected; do not connect and do not use as feed through sda 38 input/output i 2 c-bus serial data input and output scl 39 input i 2 c-bus serial clock input clk 40 input/output external clock input and internal clock output v dd 41 supply supply voltage sync 42 input/output cascade synchronization input and output (active low) osc 43 input enable input for internal oscillator a0 to a2 44 to 46 input subaddress counter input 0 to 2 sa0 47 input i 2 c-bus slave address input 0 v ss 48 supply ground supply voltage v lcd 49 input lcd supply voltage s0 to s30 50 to 80 output lcd segment output 0 to 30
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 6 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 7. functional description the pca8534a is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to four backplanes and up to 60 segments. the possible display configurations of the pca8534a depend on the number of active backplane outputs required. a selection of display configurations is shown in ta b l e 4 . all of these configurations can be implem ented in the typical system shown in figure 3 . the host microprocessor or microcontroller maintains the 2-line i 2 c-bus communication channel with the pca8534a. biasing voltages for the multiplexed lcd wa veforms are generated internally, removing the need for an external bias generator. the internal oscillator is selected by connecting pin osc to v ss . the only other connections required to complete the system are the power supplies (v dd , v ss , and v lcd ) and the lcd panel selected for the application. 7.1 power-on reset (por) at power-on the pca8534a resets to a default starting condition: ? all backplane and segment outputs are set to v lcd ? the selected drive mode is: 1:4 multiplex with 1 ? 3 bias ? blinking is switched off ? input and output bank selectors are reset ? the i 2 c-bus interface is initialized table 4. selection of display configurations number of 7-segment alphanumeric 14-segment alphanumeric dot matrix backplanes elements digits indicator symbols characters indicator symbols 4 240 30 30 16 16 240 (4 60) 3 180 22 26 12 12 180 (3 60) 2 120 15 15 8 8 120 (2 60) 160711 44 60 (1 60) fig 3. typical system configuration host micro- processor/ micro- controller r t r 2c b sda scl osc 60 segment drives 4 backplanes lcd panel (up to 240 elements) pca8534a a0 a1 a2 sa0 v dd v ss v ss v dd v lcd 013aaa27 0
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 7 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates ? the data pointer and the subaddress counter are cleared (set to logic 0) ? the display is disabled remark: do not transfer data on the i 2 c-bus after a power-on for at least 1 ms to allow the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider of three series resistors conn ected between pins v lcd and v ss . the center resistor is bypassed by switch if the 1 ? 2 bias voltage level for the 1:2 mult iplex drive mode configuration is selected. 7.3 lcd voltage selector the lcd voltage selector coordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the mode-set command from the command decoder. the biasing configurations that apply to the preferred modes of operatio n, together with the biasing characteristics as functions of v lcd and the resulting discrimina tion ratios (d) are given in ta b l e 5 . a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode a suitable choice is v lcd >3v th . multiplex drive modes of 1:3 and 1:4 with 1 ? 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 ? 2 bias a = 2 for 1 ? 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode table 5. biasing characteristics lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 1:2 multiplex 2 3 1 ? 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 ? 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 ? 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 ? 3 0.333 0.577 1.732 v off rms () v lcd ------------------------ - v on rms () v lcd ----------------------- - d v on rms () v off rms () ------------------------ - = 1 1a + ------------ - v on rms () a 2 2a n ++ n 1a + () 2 ----------------------------- - v lcd =
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 8 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 ? 2 bias is and the discrimination for an lcd drive mode of 1:4 multiplex with 1 ? 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 ? 2 bias): ? 1:4 multiplex ( 1 ? 2 bias): these compare with when 1 ? 3 bias is used. it should be noted that v lcd is sometimes referred as the lcd operating voltage. v off rms () a 2 2a ? n + n 1a + () 2 ----------------------------- - v lcd = d v on rms () v off rms () ---------------------- - a1 + () 2 n 1 ? () + a1 ? () 2 n 1 ? () + ------------------------------------------- - == 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms () 2.449v off rms () == v lcd 43 () 3 --------------------- - 2.309v off rms () == v lcd 3v off rms () =
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 9 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in figure 4 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v off(rms) = 0 v. fig 4. static driv e mode waveforms mgl745 v ss v lcd v ss v lcd v ss v lcd v lcd ? v lcd ? v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 10 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 7.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pca8534a allows the use of 1 ? 2 bias or 1 ? 3 bias in this mode as shown in figure 5 and figure 6 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.354v lcd . fig 5. waveforms for the 1:2 multiplex drive mode with 1 ? 2 bias mgl746 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd / 2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd / 2 v lcd / 2 v lcd / 2 ? v lcd ? v lcd ? v lcd / 2 ? v lcd / 2 s n sn+1 t fr
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 11 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 6. waveforms for the 1:2 multiplex drive mode with 1 ? 3 bias mgl747 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd ? v lcd 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 s n s n+1 t fr v ss v lcd 2v lcd / 3 v lcd / 3
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 12 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies, as shown in figure 7 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 7. waveforms for the 1:3 multiplex drive mode with 1 ? 3 bias mgl748 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 (a) waveforms at driver. bp2 s n s n+1 s n+2 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 13 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 8 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.577v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:4 multiplex drive mode with 1 ? 3 bias mgl749 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 v ss v lcd 2v lcd / 3 v lcd / 3 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd 0 v v lcd 2v lcd / 3 ? 2v lcd / 3 v lcd / 3 ? v lcd / 3 ? v lcd v ss v lcd 2v lcd / 3 v lcd / 3
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 14 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 7.5 oscillator the internal logic and the lcd drive signals of the pca8534a are timed by the frequency f clk , which equals either the bu ilt-in oscillator frequency f osc or the external clock frequency f clk(ext) . the clock frequency f clk determines the lcd frame frequency (f fr ). 7.5.1 internal clock the internal oscillator is enable d by connecting pin osc to pin v ss . in this case, the output from pin clk is the clock signal for any cascaded pca8534a in the system. 7.5.2 external clock pin clk is enabled as an external clock input by connecting pin osc to v dd . the lcd frame signal frequency is determined by the clock frequency (f clk ). a clock signal must always be supplied to th e device; removing the clock may freeze the lcd in a dc state, which is no t suitable for the liquid crystal. 7.6 timing the pca8534a timing controls the internal da ta flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the correct timing relationship between each pca8534a in the system is maintained by the synchronization signal at pin sync . the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency is a fixed division of the clock frequ ency from either the internal or an external clock. 7.7 display register the display register holds the display data while the corresponding multiplex signals are generated. 7.8 segment outputs the lcd drive section includes 60 segment outputs (s0 to s59) which should be connected directly to the lcd. the segment output signals are generated based on the multiplexed backpla ne signals and with data resident in the display register. when less than 60 segment outputs are required, the unused segment outputs must be left open-circuit. 7.9 backplane outputs the lcd drive section includes four backplane outputs: bp0 to bp3. the backplane output signals are generated based on the selected lcd drive mode. ? in 1:4 multiplex drive mode: bp0 to bp3 must be connected directly to the lcd. table 6. lcd frame frequencies frame frequency nominal frame frequency (hz) 64 f fr f clk 24 ------- - =
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 15 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates if less than four backplane outputs are required the unused outputs can be left as an open-circuit. ? in 1:3 multiplex drive mode: bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied togethe r to give enhanced drive capabilities. ? in 1:2 multiplex drive mode: bp0 and bp2, bp1 and bp3 respectively carry the same signals and can also be paired to increase the drive capabilities. ? in static drive mode: the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 display ram the display ram is a static 60 4-bit ram which stores lcd data. there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements ? the ram columns and the segment outputs ? the ram rows and the backplane outputs. logic 1 in the ram bit map indicates the on- state of the corresponding lcd segment, logic 0 indicates the off-state. the display ram bit map, figure 9 , shows the rows 0 to 3 which correspond with the backplane outputs bp0 to bp3, and the columns 0 to 59 which correspond with the segment outputs s0 to s59. in multiplexed lcd applications the segment data of the first, second, third and fourth row of the display ram are time-multiplexed with bp0, bp1, bp2, and bp3 respectively. when display data is transmitted to the pca8 534a the display bytes received are stored in the display ram in accordance with the se lected lcd drive mode. the data is stored as it arrives and does not wait for an ackno wledge cycle as with the commands. depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in figure 10 ; the ram filling organization depicted applies equally to other lcd types. the display ram bitmap shows the direct relationship between the display ram column and the segment outputs; and between the bits in a ram row and the backplane outputs. fig 9. display ram bit map 0 0 1 2 3 1234 5556575859 display ram addresses (columns)/segment outputs (s) display ram bits (rows)/ backplane outputs (bp) 001aah61 7
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 16 of 44 nxp semiconductors pca8534a universal lcd driver for low multiplex rates x = data bit unchanged. fig 10. relationship between lcd layout, drive mode, display ram storage order, and display data transmitted over the i 2 c-bus 001aaj64 6 acbdpf egd msb lsb bdpcadgfe msb lsb abfgecddp msb lsb cba f geddp msb lsb drive mode static 1:2 multiplex 1:3 multiplex 1:4 multiplex lcd segments lcd backplanes display ram filling order transmitted display byte bp0 bp0 bp1 bp0 bp1 bp2 bp1 bp2 bp3 bp0 n c x x x 0 1 2 3 b x x x a x x x f x x x g x x x e x x x d x x x dp x x x n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 rows display ram rows/backplane outputs (bp) byte1 columns display ram address/segment outputs (s) n a b x x 0 1 2 3 f g x x e c x x d dp x x n + 1 n + 2 n + 3 byte1 byte2 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n b dp c x 0 1 2 3 a d g x f e x x n + 1 n + 2 byte1 byte2 byte3 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) n + 1 n a c b dp 0 1 2 3 f e g d byte1 byte2 byte3 byte4 byte5 rows display ram rows/backplane outputs (bp) columns display ram address/segment outputs (s) s n+2 s n+3 s n+1 s n dp a f b g e c d s n+2 s n+1 s n+7 s n s n+3 s n+5 s n+6 s n+4 dp a f b g e c d s n s n+1 s n+2 dp a f b g e c d s n+1 s n dp a f b g e c d
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 17 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates the following applies to figure 10 : ? static mode: the eight transmitted data bits are placed in row 0 to eight successive display ram addresses. ? 1:2 multiplex mode: the eight transmitted data bits are placed in row 0 and 1 to four successive display ram addresses. ? 1:3 multiplex mode: the eight transmitted data bits are placed in row 0, 1, and 2 to three successive addresses. ho wever, bit 2 of the third address is left unchanged. this last bit can, if necessary, be controlled by an additional transfer to this address but avoid overriding adjacent data because full bytes are always transmitted. ? 1:4 multiplex mode: the eight transmitted data bits are placed in row 0, 1, 2, and 3 to two successive display ram addresses. 7.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the load-data-pointer command (see ta b l e 1 2 ). following this command, an arriving data byte is stored at the displa y ram address indicated by the data pointer. the filling order is shown in figure 10 . after each byte is stored, the content of the da ta pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight ? in 1:2 multiplex drive mode by four ? in 1:3 multiplex drive mode by three ? in 1:4 multiplex drive mode by two if an i 2 c-bus data access is terminated early then the state of the data pointer is unknown. the data pointer should be re-written prior to further ram accesses. 7.12 subaddress counter the storage of display data is conditioned by the contents of the subaddress counter. storage is allowed only when the contents of the subaddress counter agree with the hardware subaddress applied to a0, a1, and a2. the subaddress counter value is defined by the device-select command (see table 13 ). if the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage ha d taken place. the subaddress counter is also incremented when the data pointer overflows. in cascaded applications each pca8534a in the cascade must be addressed separately. initially, the first pca8534a is selected by sending the device-select command matching the first device's hardware subaddress. then the data pointer is set to the preferred display ram address by sending the load-data-pointer command. once the display ram of the first pca8534a has been written, the second pca8534a is selected by sending the device-select comma nd again. this time however the command matches the second device's hardware subaddress. next the load-data-pointer command is sent to select the preferred displa y ram address of the second pca8534a.
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 18 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates this last step is very important because during writing data to the first pca8534a, the data pointer of the second pca8534a is incremented. in addition, the hardware subaddress should not be changed whilst the device is being accessed on the i 2 c-bus interface. 7.13 output bank selector the output bank selector (see ta b l e 1 4 ), selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode: all ra m addresses of row 0 are selected, followed sequentially by the contents of row 1, row 2, and then row 3. ? in 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially. ? in 1:2 multiplex mode: rows 0 and 1 are selected. ? in the static mode: row 0 is selected. the sync signal resets these sequences to the following starting points: row 3 for 1:4 multiplex, row 2 for 1:3 mult iplex, row 1 for 1: 2 multiplex and row 0 for static mode. the pca8534a includes a ram bank switching f eature in the static and 1:2 multiplex drive modes. in static drive mode, the bank -select command may request the contents of row 2 to be selected for display instead of the contents of row 0. in 1:2 multiplex drive mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this enables preparation of display information in an alternative bank and the ability to switch to it once it has been assembled. 7.14 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. the input bank selector functions independe ntly to the output bank selector. 7.15 blinker the display blinking capabilitie s of the pca8534a are very versatile. the whole display can be blinked at frequencies set by the blink-select command (see ta b l e 1 5 ). the blinking frequencies are fractions of the cloc k frequency. the ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see ta b l e 7 ).
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 19 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates an additional feature is for the arbitrary sele ction of lcd segments to be blinked. this applies to the static and 1:2 multiplex dr ive modes and is implemented without any communication overheads. using the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blinking frequency. this mode can also be specified by the b link-select command. in the 1:3 and 1:4 multiplex modes, where no alternate ram bank is available, groups of lcd segments can be blinked by selectively changing the display ram data at fixed time intervals. if the entire display needs to be blinked at a frequency other than the nominal blinking frequency, this can be done using the mode-set command to set and reset the display enable bit e at the required rate (see ta b l e 11 ). 7.16 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.16.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 11 ). table 7. blink frequencies assuming that f clk = 1536 hz. blink mode operating mode ratio blink frequency off - blinking off 12 hz 21 hz 3 0.5 hz f blink f clk 768 -------- - = f blink f clk 1536 ----------- - = f blink f clk 3072 ----------- - = fig 11. bit transfer mba60 7 data line stable; data valid change of data allowed sda scl
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 20 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 7.16.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition - s. a low-to-high transition of the data line while the clock is high is defined as the stop condition - p (see figure 12 ). 7.16.3 system configuration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 13 ). 7.16.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? a master receiver must generate an acknowle dge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). fig 12. definition of start and stop conditions mbc62 2 sda scl p stop condition sda scl s start condition fig 13. system configuration mga80 7 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 21 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 14 . 7.16.5 i 2 c-bus controller the pca8534a acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pca8534a are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferre d command data and on the hardware subaddress. in single device applications, the hardware subaddress inputs a0, a1, and a2 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1, and a2 are tied to v ss or v dd using a binary coding scheme, so that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 7.16.6 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 7.16.7 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are used to address the pca8534a. the entire i 2 c-bus slave address byte is shown in ta b l e 8 . fig 14. acknowledgement of the i 2 c-bus mbc60 2 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master table 8. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011100sa0r/w
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 22 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates the pca8534a is a write-only device and will not re spond to a read access, therefore bit 0 should always be logic 0. bit 1 of the sl ave address byte that a pca8534a will respond to, is defined by the leve l tied to its sa0 input (v ss for logic 0 and v dd for logic 1). having two reserved slave addresses allows the following on the same i 2 c-bus: ? up to 16 pca8534a for very large lcd applications ? the use of two types of lcd multiplex drive the i 2 c-bus protocol is shown in figure 15 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of two possible pca8534a slave addresses available. all pca8534a whose sa0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. this i 2 c-bus transfer is ignored by all pca8534a whose sa0 inputs are set to the alternative level. after an acknowledgement, one or more command bytes follow that define the status of each addressed pca8534a. the last command byte sent is identified by resetting its most signif icant bit, continuation bit co (see figure 16 ). the command bytes are also acknowledged by all addressed pca8534a on the bus. fig 15. i 2 c-bus protocol examples a) transmit two bytes of ram data mgl75 2 s a 0 s 01110 0 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s a 0 s 01110 0 01 0 a a a p ram data a b) transmit two command bytes command s a 0 s 01110 0 10 0 a a a p command a a c) transmit one command byte and two ram date bytes command s a 0 s 01110 0 10 00 01 0 a a a p ram data a ram data a a c o r s fig 16. control byte format mgl753 not relevant co 76 543210 rs msb lsb
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 23 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates the command bytes and control bytes are also acknowledged by all addressed pca8534a connected to the bus. the display bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated. the acknowledgement after each byte is made only by the (a0, a1 and a2) addressed pca8534a. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart i 2 c-bus access. 7.17 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. there are five commands: table 9. control byte description bit symbol value description 7co continue bit 0 last control byte 1 control bytes continue 6rs register selection 0 command register 1 data register 5 to 0 - not relevant table 10. definition of commands command operation code reference bit 7 6 5 4 3 2 1 0 mode-set 1 1 0 0 e b m1 m0 ta b l e 11 load-data-pointer 0 p6 p5 p4 p3 p2 p1 p0 ta b l e 1 2 device-select 1 1 1 0 0 a2 a1 a0 ta b l e 1 3 bank-select 111110i o ta b l e 1 4 blink-select 1 1 1 1 0 a bf1 bf0 ta b l e 1 5
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 24 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates [1] the bank select command has no effect in 1:3 or 1:4 multiplex drive modes. table 11. mode-set command bit description bit symbol value description 7 to 4 - 1100 fixed value 3e display status the possibility to disable the di splay allows implementation of blinking under external control 0 disabled 1 enable 2b lcd bias configuration 0 1 ? 3 bias 1 1 ? 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; 1 backplane 10 1:2 multiplex; 2 backplanes 11 1:3 multiplex; 3 backplanes 00 1:4 multiplex; 4 backplanes table 12. load-data-pointer command bit description bit symbol value description 7 - 0 fixed value 6 to 0 p[6:0] 000 0000 to 011 1011 7-bit binary value of 0 to 59 table 13. device-select command bit description bit symbol value description 7 to 3 - 11100 fixed value 2 to 0 a[2:0] 000 to 111 3-bit binary value of 0 to 7 table 14. bank-select command bit description bit symbol value description static 1:2 multiplex [1] 7 to 2 - 111110 fixed value 1i input bank selection : storage of arriving display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3 0o output bank selection : retrieval of lcd display data 0 ram bit 0 ram bits 0 and 1 1 ram bit 2 ram bits 2 and 3
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 25 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates [1] only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes. [2] the blink frequencies are shown in table 7 . 7.18 display controller the display controller executes the command s identified by the command decoder. it contains the status registers of the pc a8534a and coordinates their effects. the controller also loads display data into the display ram as required by the storage order. table 15. blink-select command bit description bit symbol value description 7 to 3 - 1111 0 fixed value 2a blink mode selection 0 normal blinking [1] 1 blinking by alternating display ram banks 1 to 0 bf[1:0] blink frequency selection [2] 00 off 01 1 10 2 11 3
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 26 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 8. internal circuitry fig 17. device protection diagram sa0 v dd v dd v ss v ss v lcd v ss sda 001aah61 5 v ss scl v ss clk v dd v ss osc v dd v ss sync v dd v ss a0, a1, a2 v dd v ss bp0, bp1, bp2, bp3 v lcd v ss s0 to s59 v lcd v ss
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 27 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 9. limiting values [1] pins sda, scl, clk, sync , sa0, osc and a0 to a2. [2] pins s0 to s59 and bp0 to bp3. [3] pass level; human body model (hbm), according to ref. 5 ? jesd22-a114 ? . [4] pass level; machine model (mm), according to ref. 6 ? jesd22-a115 ? . [5] pass level; charged-device model (cdm), according to ref. 7 ? jesd22-c101 ? [6] pass level; latch-up testing according to ref. 8 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [7] according to the nxp store and transport requirements (see ref. 10 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 c to +45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 16. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v i dd supply current ? 50 +50 ma v lcd lcd supply voltage ? 0.5 +7.5 v i dd(lcd) lcd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma v i input voltage [1] ? 0.5 +6.5 v i i input current [1] ? 10 +10 ma v o output voltage [1] ? 0.5 +6.5 v [2] ? 0.5 +7.5 v i o output current [1] [2] ? 10 +10 ma p tot total power dissipation - 400 mw p/out power dissipation per output - 100 mw v esd electrostatic discharge voltage hbm [3] - 3000 v mm [4] - 200 v cdm [5] - 1000 v i lu latch-up current [6] -200ma t stg storage temperature [7] ? 65 +150 c t oper operating temperature ? 40 +85 c
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 28 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 10. static characteristics [1] lcd outputs are open circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [2] for typical values, see figure 18 . [3] for typical values, see figure 19 . [4] not tested, design specification only. [5] outputs measured indi vidually and sequentially. table 17. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 2.5 - 6.5 v i dd supply current f clk(ext) = 1536 hz [1] [2] --20 a i dd(lcd) lcd supply current f clk(ext) = 1536 hz [1] [3] --60 a logic v i input voltage v ss ? 0.5 v dd + 0.5 v v il low-level input voltage on pins clk, sync , osc, a0 to a2 and sa0 v ss -0.3v dd v v ih high-level input voltage on pins clk, sync , osc, a0 to a2 and sa0 0.7v dd -v dd v v por power-on reset voltage 1.0 1.3 1.6 v i ol low-level output current output sink current; v ol = 0.4 v; v dd = 5 v; on pins clk and sync 1-- ma i oh high-level output current output source current; v oh = 4.6 v; v dd = 5 v; on pin clk 1-- ma i l leakage current v i = v dd or v ss ; on pins sa0, a0 to a2 and clk ? 1-+1 a v i = v dd ; on pin osc ? 1-+1 a c i input capacitance [4] --7pf i 2 c-bus; pins sda and scl v i input voltage v ss ? 0.5 - 5.5 v v il low-level input voltage pin scl v ss -0.3v dd v pin sda v ss -0.2v dd v v ih high-level input voltage 0.7v dd -5.5 v i ol low-level output current v ol = 0.4 v; v dd = 5 v; on pin sda 3 - - ma i l leakage current v i = v dd or v ss ? 1-+1 a c i input capacitance [4] --7pf lcd outputs output pins bp0, bp1, bp2 and bp3 v bp voltage on pin bp c bpl = 35 nf ? 100 - +100 mv r bp resistance on pin bp v lcd = 5 v [5] -1.510k output pins s0 to s59 v s voltage on pin s c sgm = 35 nf ? 100 - +100 mv r s resistance on pin s v lcd = 5 v [5] - 6.0 13.5 k
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 29 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates t amb =30 c; 1:4 multiplex; v lcd = 6.5 v; f clk(ext) = 1.536 khz; all ram written with logic 1; no display connected; i 2 c-bus inactive. fig 18. typical i dd with respect to v dd t amb =30 c; 1:4 multiplex; f clk(ext) = 1.536 khz; all ram written with logic 1; no display connected. fig 19. typical i dd(lcd) with respect to v lcd v dd (v) 26 5 34 001aal523 2 3 1 4 5 i dd ( a) 0 001aal524 v lcd (v) 39 7 5 8 12 4 16 20 i dd(lcd) ( a) 0
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 30 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 11. dynamic characteristics [1] typical output (duty cycle = 50 %). [2] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 18. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit clock internal: output pin clk f osc oscillator frequency v dd = 5 v [1] 960 1536 3046 hz external: input pin clk f clk(ext) external clock frequency v dd = 5 v 797 1536 3046 hz t clk(h) high-level clock time 130 - - s t clk(l) low-level clock time 130 - - s synchronization: input pin sync t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 1 - - s outputs: pins bp0 to bp3 and s0 to s59 t pd(drv) driver propagation delay v lcd = 5 v - - 30 s i 2 c-bus: timing [2] pin scl f scl scl frequency - - 400 khz t low low period of the scl clock 1.3 - - s t high high period of the scl clock 0.6 - - s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - s t su;sto set-up time for stop condition 0.6 - - s t hd;sta hold time (repeated) start condition 0.6 - - s t su;sta set-up time for a repeated start condition 0.6 - - s t r rise time of both sda and scl signals - - 0.3 s t f fall time of both sda and scl signals - - 0.3 s c b capacitive load for each bus line - - 400 pf t w(spike) spike pulse width - - 50 ns
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 31 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates fig 20. driver timing waveforms fig 21. i 2 c-bus timing waveforms 001aah618 0.7v dd 0.3v dd 0.7v dd 0.3v dd 1 / f clk t pd(sync_n) t pd(sync_n) t clk(h) t clk(l) sync clk 0.5 v 0.5 v t pd(drv) bp0 to bp3, and s0 to s59 t sync_nl (v dd = 5 v) sda mga72 8 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 32 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 12. application information 12.1 cascaded operation large display configurations of up to 16 pca8534a can be recognized on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1, and a2) and the programmable i 2 c-bus slave address (sa0). if cascaded pca8534a are synchronized, they can share the backplane signals from one of the devices in the cascade. this is cost-effective in large lcd applications because the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other pca8 534a in the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see figure 22 ). table 19. addressing cascaded pca8534a cluster bit sa0 pin a2 pin a1 pin a0 device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 33 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates the sync line is provided to maintain the corr ect synchronization between all cascaded pca8534a. synchronization is guaranteed after a power-on reset. the only time that sync is likely to be needed is if synchroniz ation is accidentally lost (e.g. by noise in adverse electrical environments or by defi ning a multiplex mode when pca8534a with different sa0 levels are cascaded). sync is organized as an input/output pin. the output selection is realized as an open-drain driver with an internal pull-up resistor. a pca8534a asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. if synchronization in the cascade is lost, it is restored by the first pca853 4a to assert sync . the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the pca8534a are shown in figure 23 . fig 22. cascaded pca8534a configuration host micro- processor/ micro- controller sda scl clk osc sync 60 segment drives 4 backplanes 60 segment drives lcd panel pca8534a a0 a1 a2 sa0 v ss v ss v ss v dd v dd v lcd v lcd v dd v lcd 013aaa27 1 sda scl sync clk osc bp0 to bp3 (open-circuit) a0 a1 a2 sa0 pca8534a bp0 to bp3 r t r 2c b
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 34 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates the contact resistance between the sync pins of cascaded devices must be controlled. if the resistance is too high, the device w ill not be able to syn chronize properly. ta b l e 2 0 shows the maximum contact resistance values. the pca8534a can always be cascaded with other devices of the same type or conditionally with other devices of the same fa mily. this allows opti mal drive selection for a given number of pixels to display. figure 20 and figure 23 show the timing of the synchronization signals. fig 23. synchronization of the cascade for various pca8534a drive modes table 20. sync contact resistance number of devices maximum contact resistance 2 6000 3 to 5 2200 6 to 10 1200 11 to 16 700 t fr = f fr 1 bp0 sync bp0 (1/2 bias) sync bp0 (1/3 bias) (a) static drive mode. (b) 1:2 multiplex drive mode. (c) 1:3 multiplex drive mode. (d) 1:4 multiplex drive mode. bp0 (1/3 bias) sync sync bp0 (1/3 bias) mgl755
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 35 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates in a cascaded configuration only one pca8534a master must be used as clock source. all other pca8534a in the cascade must be co nfigured as slave such that they receive the clock from the master. if an external clock source is used, all pca8534a in the cascade must be configured such as to receive the clock from that exte rnal source (pin osc connected to v dd ). thereby it must be ensured that the clock tree is desi gned such that on all pca8534a the clock propagation delay from the clock source to all pca8534a in the cascade is as equal as possible since otherwise synchronization artefacts may occur. in mixed cascading configurations , care has to be taken that the specifications of the individual cascaded devices are met at all times.
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 36 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 13. package outline fig 24. package outline sot315-1 (lqfp80) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1) (1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale l qfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315 -1
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 37 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 14. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 15. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 38 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 15.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 15.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 25 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 1 and 22 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 25 . table 21. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 22. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 39 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 25. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 40 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 16. abbreviations table 23. abbreviations acronym description aec automotive electronics council cmos complementary metal-oxide semiconductor cdm charged device model dc direct current hbm human body model i 2 c inter-integrated circuit ic integrated circuit lcd liquid crystal display lsb least significant bit mm machine model msb most significant bit msl moisture sensitivity level pcb printed-circuit board por power-on reset ram random access memory rc resistance and capacitance rms root mean square scl serial clock line sda serial data line smd surface-mount device
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 41 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 17. references [1] an10365 ? surface mount reflow soldering description [2] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [3] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [4] ipc/jedec j-std-020d ? moisture/reflow sensitiv ity classification for nonhermetic solid state surface mount devices [5] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [6] jesd22-a115 ? electrostatic discharge (esd) se nsitivity testing machine model (mm) [7] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [8] jesd78 ? ic latch-up test [9] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [10] nx3-00092 ? nxp store and transport requirements [11] snv-fa-01-02 ? marking formats integrated circuits [12] um10204 ? i 2 c-bus specification and user manual 18. revision history table 24. revision history document id release date data sheet status change notice supersedes pca8534a_2 20100601 product data sheet - pca8534a_1 modifications: ? corrected marking code in ta b l e 2 pca8534a_1 20100415 product data sheet - -
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 42 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pca8534a_2 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 02 ? 1 june 2010 43 of 44 nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca8534a universal lcd driver fo r low multiplex rates ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 1 june 2010 document identifier: pca8534a_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 power-on reset (por) . . . . . . . . . . . . . . . . . . 6 7.2 lcd bias generator . . . . . . . . . . . . . . . . . . . . . 7 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . . 9 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 7.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 10 7.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 12 7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 13 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.11 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.12 subaddress counter . . . . . . . . . . . . . . . . . . . . 17 7.13 output bank selector . . . . . . . . . . . . . . . . . . . 18 7.14 input bank selector . . . . . . . . . . . . . . . . . . . . . 18 7.15 blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.16 characteristics of the i 2 c-bus. . . . . . . . . . . . . 19 7.16.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16.2 start and stop conditions . . . . . . . . . . . . . 20 7.16.3 system configuration . . . . . . . . . . . . . . . . . . . 20 7.16.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 21 7.16.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.7 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 7.17 command decoder . . . . . . . . . . . . . . . . . . . . . 23 7.18 display controller . . . . . . . . . . . . . . . . . . . . . . 25 8 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 10 static characteristics. . . . . . . . . . . . . . . . . . . . 28 11 dynamic characteristics . . . . . . . . . . . . . . . . . 30 12 application information. . . . . . . . . . . . . . . . . . 32 12.1 cascaded operation . . . . . . . . . . . . . . . . . . . . 32 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 36 14 handling information . . . . . . . . . . . . . . . . . . . 37 15 soldering of smd packages . . . . . . . . . . . . . . 37 15.1 introduction to soldering. . . . . . . . . . . . . . . . . 37 15.2 wave and reflow soldering. . . . . . . . . . . . . . . 37 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 38 15.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 38 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40 17 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 41 19 legal information . . . . . . . . . . . . . . . . . . . . . . 42 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 42 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 42 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 20 contact information . . . . . . . . . . . . . . . . . . . . 43 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

▲Up To Search▲

Price & Availability of PCA8534AH-Q900

	To Download PCA8534AH-Q900 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .